In integrated circuit manufacturing, large scale integration (LSI) or very large scale integration (VLSI) techniques may be used to fabricate complex electrical circuits on a semiconductor substrate. The design and manufacture of many devices have been made possible by reductions in circuit dimensions. A photolithography step is frequently utilized to transfer a pattern for an electrical circuit layer from a photomask to a silicon wafer. Various photolithographic systems use a variety of transfer techniques, including step-and-repeat processes, to gradually transfer a mask pattern from a macroscopic prototype to a microscopic implementation.
Alignment marks are typically created in the silicon substrate and/or in layers of material formed thereon as reference coordinate(s) to improve overlay measurement accuracy and/or to compensate for processing inaccuracies. The alignment marks are created by various processing steps and may be located in the scribe lines of the semiconductor wafer. The scribe lines are the strips of a wafer between integrated circuit (IC) dice where the semiconductor wafer is cut. This area generally is not used for functional IC componentry because such componentry may be destroyed during cutting.
Global alignments between mask layers are generally done by measuring contrasts in light intensities reflected back from the steps created by the elevated portions of the alignment marks. Generally, as long as the step heights in the alignment marks are preserved through subsequent processing steps, global alignment in masking steps (compared to the masking layers) can be achieved. As critical dimensions (CD) of individual transistors transferred from a masked pattern shrink, global planarization at the wafer level becomes advantageous.
Chemical Mechanical Polishing (CMP) is an industry-recognized process. The CMP process is used to achieve global planarization (planarization of the entire wafer). Both chemical and mechanical forces result in a polished wafer. CMP apparatuses generally include an automated rotated polishing platen and a wafer holder. The wafer holder is generally used to hold the wafer in place while the platen exerts a force on the wafer. At the same time, the wafer and platen may be independently rotated. A polishing slurry may be applied to the polishing pad and/or the wafer. The polishing pad contacts relatively high spots on the wafer and, in conjunction with the slurry, removes material from the relatively high spots on the wafer. Planarization occurs because the high spots on the wafer polish faster than low spots on the wafer. Thus, the relatively high portions of the wafer are smoothed to a uniform level faster than the other, relatively low portions of the wafer.
After CMP, the various portions of the wafer, including the alignment marks, may become covered with a relatively flat material. Planarizing the alignment marks or materials covering the alignment marks may create problems for providing proper alignment during subsequent masking steps.
One typical way to get around planarizing problems is to perform a process called "open frame" which reproduces the step height in the alignment marks. This, however, may introduce extra and/or costly steps in the fabrication of the wafer.
Tungsten deposition and the CMP process are typically used to fabricate tungsten contacts. Thus, tungsten CMP (WCMP) is one notable variation of the CMP process. Tungsten is generally preferred to aluminum for contacts due to step coverage problems that arise in high aspect ratio holes during aluminum deposition.
After tungsten deposition, the original alignment marks may be covered with a layer of tungsten film. The grain quality of the tungsten film typically produces poor light reflection quality and, therefore, makes alignment of the mask pattern difficult to control.
Furthermore, WCMP (or any type of CMP) uses particulate matter (usually in the form of a silica and/or alumina slurry) to polish wafers. Such particulate matter (and/or particulate matter generated by CMP) may become trapped between structural features of the alignment marks. In addition, alignment mark structures are typically located in areas of the wafer not having other structural features nearby (e.g., an open frame die or a scribe line). Consequently, the outermost edge of an alignment mark structure being polished may be polished at a slightly faster rate or at a slightly greater pressure than the remainder of the structure, thus increasing the risk of changing the angle of light reflected from the mark, in turn increasing the likelihood and magnitude of measurement errors. As a result, alignment marks may be rendered ineffective after CMP, and particularly after the WCMP process.